Hi! I'm Christof Schlaak,

CV

a fourth year PhD student at the Institute for Computing Systems Architecture (ICSA) at the University of Edinburgh. I'm working on a functional language for high-level synthesis of hardware accelerators (read more). I am a member of the Compiler and Architecture Design (CArD) group. My research is supervised by Christophe Dubach from McGill University and Aaron Smith (MSR) and is supported with a PhD scholarship by Microsoft Research.

📧 christof.schlaak (a t) ed.ac.uk
📍 University of Edinburgh,
Informatics Forum, room 1.05/2
github.com/cschlaak
dblp.uni-trier.de

background

🎓	2014	\|	B.Sc. Informatics in Oldenburg, Germany
🎓	2016	\|	M.Sc. Informatics with focus on embedded systems in Oldenburg, Germany
🔍	2018	\|	Researcher at OFFIS - Institute for Information Technology in the group Safety & Security Oriented Design Methods & Processes
📝	now	\|	PhD under construction …

research interests

FPGA, concurrency, high-performance computing, performance portability, low-power computing, code generation, high-level programming, compiler, hardware design, neural networks

talks

Memory-Aware Functional IR for Higher-Level Synthesis of Accelerators
(Jun 20, 2022)
Talk at the Conference on High-performance Embedded Architecture and Compilation (HiPEAC 2022) in Budapest, Hungary.
Optimizing Data Reshaping Operations in Functional IRs for High-Level Synthesis
(Jun 14, 2022)
Talk at the 23rd ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2022) in San Diego, CA, United States.
Optimizing Data Reshaping Operations in Functional IRs for High-Level Synthesis
(Jun 8, 2022)
Talk at the Popco seminar at McGill University in Montreal, Canada.
Functional Languages for High-Level Synthesis
(Apr 11, 2022)
Invited lecture for the Computer Architecture course (ECSE 425, Winter 2022) of Prof. Amin Emad at McGill University in Montreal, Canada.
High-level Synthesis of Neural Networks for FPGAs with Lift 🗎
(Dec 9-11, 2019)
Poster at Google's 7th Compiler and Programming Language Summit 2019 in Munich, Germany.
Synthesising Neural Networks on FPGAs with Lift
(Sep 20, 2019)
Talk at the Facebook AI Systems Faculty Summit 2019 at Facebook HQ in Menlo Park, CA, United States.
High-level Synthesis of Neural Networks for FPGAs with Lift 🗎
(Jul 14-20, 2019)
Poster at the Fifteenth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2019) in Fiuggi, Italy.
High-level Synthesis of Neural Networks for FPGAs with Lift 🗎
(Apr 16-18, 2019)
Lightning talk and poster at the HiPEAC Computer Systems Week (CSW Spring 2019) in Edinburgh, United Kingdom.

publications

2022

Optimizing Data Reshaping Operations in Functional IRs for High-Level Synthesis 🗎
Christof Schlaak, Tzung-Han Juang and Christophe Dubach
Proceedings of the 23rd ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2022)

Memory-Aware Functional IR for Higher-Level Synthesis of Accelerators 🗎
Christof Schlaak, Tzung-Han Juang and Christophe Dubach
ACM Transactions on Architecture and Code Optimization (TACO), Vol. 19, No. 2, Article 16.

2018

Design Validation for Embedded Multi-core Systems in the Context of ISO 26262 🗎
Benedikt Bauer, Jan Steffen Becker, Thomas Peikenkamp, Christof Schlaak and Ingo Stierand
Workshop on Software Engineering for Applied Embedded RealTime Systems (SEERTS).

2017

Power and Execution Time Measurement Methodology for SDF Applications on FPGA-based MPSoCs 🗎
Christof Schlaak, Maher Fakih and Ralf Stemmer
Proceedings of the Workshop on High Performance Energy Efficient Embedded Systems (HIP3ES). Collocated with HIPEAC 2017 Conference.